中英互译

buried layer

基本释义

An on-resistance self limitation 2-d model for integrated power devices with buried layer is proposed.
对具有埋层结构的集成大功率器件提出了导通电阻自限制二维模型。
A buried layer (7) is provided as a collector connection area which joins the collector contact (6) to a collector area (14).
埋层(7)作为集电极连接区域提供，用于连接集电极接触(6)和集电极区(14)。
Using the derived amplitude and phase expressions, the experimental data of the three-layer sample are fitted. The thickness of the buried layer in the sample is calculated.
用推导的振幅和位相表达式拟合三层样品的实验数据，并计算出中间层的厚度。